Hi, I’m Pavan

Boot Software Engineer, NVIDIA

Specialized in the end-to-end enablement of bootloader features throughout the entire chipset lifecycle, delivering robust platform stability and scalable, production-ready firmware architectures. Extensive hands-on experience with NVIDIA Tegra and Qualcomm Snapdragon chipsets in mobile, modem, automotive, and Jetson platforms.

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About Me

“Not in doing what you like, but in liking what you do is the secret of happiness.” — J.M. Barrie

Until now, in my life, I have changed from active moments with a lot of variety, challenges and improvisations, to moments of tranquility and stability, being difficult to stay in a place for a long time. I consider myself a tolerant and respectful person with an open mind and quite honest. I really like to listen to people's stories and backgrounds and their different experiences around the world.

Interests & Hobbies

Work Experience

MAR 2024 - Present

Boot Software Engineer — Nvidia India Graphics Limited, Bengaluru

Enablement of bootloader features for Tegra chipsets through full product lifecycle: pre-silicon, FPGA, silicon bring-up, and customer release.
Managed driver/module ownership in micro boot images with a focus on modularity and reuse across platforms, targets, and boards.
Developed and executed regression test cases for boot-chain features including DRAM ECC, memory scrubbing, page retirement, carveout settings, firmware loading, and fuse alias.
Initialized core subsystems including MSS, iGPU, and FSI in early boot/software integration phases.
Collaborated with cross-functional teams to identify and resolve system-level bugs.

MAY 2021 - FEB 2023

DDR Software Systems Associate Engineer — Qualcomm

Enabled DDR subsystem features for value-tier chipsets including Snapdragon 600 and 400 series from post-silicon to customer sample phases.
Enhanced XBL-level DDR debug tests to validate DRAM health with NAND / eMMC / UFS storage configurations.
Resolved DDR subsystem customer issues via collaboration across DDR PHY, SVE, ICB, NoC, and other teams.

MAY 2020 - AUG 2020

Interim Engineering Intern — Qualcomm

Built DDR Eye Health Classifier tool:
Developed algorithms to map DDR PHY Vref and CDC to 2D eye plot data, generated synthetic data, and used CNN to classify eye plot health.
Developed framework to report class and feature parameters for DDR eye plots on test SoCs.
Secured pre-placement offer for performance and impact.

Featured Projects

Autonomous Driving Simulator (Deep Learning)

Used OpenCV and Hough transforms for lane detection, traffic sign recognition and behavioral cloning to predict steering angles.

PV Cell Modeling & Simulation

Implemented electrical PV cell model in MATLAB Simulink, performed regression-based IV curve fitting.

Brain Tumor Detection (Genetic Algorithms)

Built pipeline using evolutionary optimization for feature selection and classification accuracy improvements.

Genome Assembly (de Bruijn Graph)

Developed genome assembly algorithm using de Bruijn graph representation and traversal techniques.

Short-term Load Forecasting (LSTM)

Modeled time-series power consumption with LSTM to reduce forecast error and optimize scheduling.

Education

IIT Varanasi

B.Tech Electrical Engineering, CGPA 8.31

Courses: AI, Deep Learning, NLP, Parallel Computing, OS, DS & Algo.

FIITJEE P U College

XII PCMB, 85.17%

Abhinava Bharathi High School

X Standard, 97.92% (School Rank 1)

Skills

DDR Firmware

System Debugging

C/C++

Python

Embedded Systems

Machine Learning

Awards & Achievements

JEE Advanced 99.7 percentile (AIR 3,192)
Karnataka Regional Mathematical Olympiad Certificate of Merit (Rank 15)
NTSE Stage 1 State Rank 18 (DSERT Karnataka)
2 Gold, 3 Silver, 7 Bronze in inter-college aquatics events
State representation in swimming and chess (2011-2014)

Contact

Email: pavanmggp@gmail.com

Location: Bengaluru, India

Current Company: Nvidia

Open to new collaborations and technical roles.

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